1. Field of the Invention
This invention relates to Dynamic Random Access Memories (DRAM) and more particularly to support circuitry and circuit configurations for such DRAM arrays for pre-charging bit lines and sensing the charge level representing digital data in a DRAM cell.
2. Description of Related Art
The sensing scheme of folded-bit-line DRAM as described in A. Bellaouar and M. Elmasry, "Low power digital VLSI design--circuits and systems", Kiuwer Academic, Chapter 6, section 6,2.13.1, p.381-383, 1995, and shown in FIGS. 1a and 1b is well known in the art. The pass transistor M.sub.p and the cell capacitor C.sub.c form the memory cells 100. The gates of the pass transistors M.sub.p are connected to the word lines WL.sub.1 115a, WL.sub.2 115b, WL.sub.3 115c, WL.sub.n-2 115d, WL.sub.n-1 115e, and WL.sub.n 115f. The sources of the pass transistors M.sub.p are connected to the primary and complementary bit lines BL 105 and BL 110. When the word line WL.sub.1 115a WL.sub.2 115b, WL.sub.3 115c, WL.sub.n-2 115d, WL.sub.n-1 115e, or WL.sub.n 115f is brought to a voltage level V.sub.h that is higher than the power supply voltage source V.sub.cc by approximately one threshold voltage V.sub.T level of the pass transistor M.sub.p, the pass transistor M.sub.p will be turned on to allow the charging and discharging of the cell capacitance C.sub.c without the voltage drop of the threshold voltage V.sub.T level of the pass transistor M.sub.p.
The N-type metal oxide semiconductor (MOS) transistors M.sub.3 and M.sub.4 form the negative sense amplifier 125a and the P-type MOS transistors M.sub.5 and M.sub.6 form the positive sense amplifier 125b. The negative sense amplifier voltage source 127, which is connected to the ground GND, and the positive sense amplifier voltage source 129, which connected to the power supply voltage source V.sub.cc, provide the necessary voltage to latch the negative sense amplifier 125a and the positive sense amplifier 125b.
The N-type MOS transistors M.sub.7, M.sub.8, and M.sub.9 form the pre-charge and equalization circuit 130. The gates of the MOS transistors M.sub.7, M.sub.8, and M.sub.9 are connected to the pre-charge and equalization control voltage source 132. The drains of the MOS transistors M.sub.7 and M.sub.8 are connected to the reference voltage source V.sub.cc /2 135. The sources of the MOS transistors M.sub.7 and M.sub.8 are connected respectively to the primary and complementary bit lines BL 105 and BL 110.
When the pre-charge and equalization control voltage source 132 is brought to a level sufficient to turn on the MOS transistors M.sub.7, M.sub.8, and M.sub.9, the primary and complementary bit lines BL 105 and BL 110 are pre-charged to the voltage level that is one half the voltage level of the power supply voltage source (V.sub.cc,/2), and the MOS transistor M.sub.9 will equalize any voltage difference between the primary and complementary bit lines BL 105 and BL 110. The pre-charging operation is the charging of the distributed capacitance of each of the primary and complementary bit lines BL 105 and BL 110 as represented by the capacitors CBL.sub.1a 107, CBL.sub.1b 108, CBL.sub.2a 112, CBL.sub.2b 113.
The MOS transistors M.sub.1, M.sub.2, M.sub.10, and M.sub.11 form the isolation circuits 120a and 120b that divide the primary and complementary bit lines BL 105 and BL 110 into segments so as to isolate the memory cells 100 from the negative and positive sense amplifiers 125a and 125b and the pre-charge and equalization circuit 130. The isolation voltage control circuit 122a is attached to the gates of the MOS transistors M.sub.1 and M.sub.2. The isolation voltage control circuit 122b is attached to the gates of the MOS transistors M.sub.10 and M.sub.11. The isolation voltage control circuit 122a and 122b will turn on or turn off the MOS transistors M.sub.1, M.sub.2, M.sub.10, and M.sub.11 selectively to connect the memory cells 100 to the negative and positive sense amplifiers 125a and 125b and the pre-charge and equalization circuit 130. The switches S.sub.1, S.sub.2, S.sub.3, and S.sub.4 are single pole single throw switches that are formed respectively by the MOS transistors M.sub.1, M.sub.2, M.sub.10, and M.sub.11. Typically, the isolation voltage control circuit 122a will turn on switches S.sub.1, S.sub.2. At the same time, the isolation voltage control circuit 122b will turn off switches S.sub.3, and S.sub.4. Or conversely, the isolation voltage control circuit 122a will turn off switches S.sub.1, S.sub.2. At this same time, the isolation voltage control circuit 122b will turn on switches S.sub.3, and S.sub.4. The isolation voltage control circuits 122a and 122b will not turn on or turn off switches S.sub.1 and S.sub.2 and switches S.sub.3, and S.sub.4 simultaneously.
FIG. 2 shows multiple rows of the DRAM cells as arranged in FIGS. 1a and 1b. The read operation begins by the isolation voltage control circuit 122a activating the switches S.sub.1 and S.sub.2 in the isolation circuit 120a to couple the segment of the primary and complementary bit lines BL 105 and BL 110 connected to the sub-array of DRAM cells 150. The isolation voltage control circuit 122b will maintain the switches S.sub.3 and S.sub.4 of the isolation circuit 120b open to isolate the segment of the primary and complementary bit lines BL 105 and BL 110 connected to the sub-array of DRAM cells 155 of the DRAM cells.
The equalization circuit 130 will be activated as described above to pre-charge the bit line capacitances 107 and 112 and equalize any voltage difference between the primary and complementary bit lines BL 105 and BL110.
A word line attached to the DRAM cells 100 that are to be read is activated. For instance, if the DRAM cells 100 attached to word line WL3 115c are to be read, the word line WL3 115c will be brought to a voltage level V.sub.h that is greater than the power supply voltage source by at least the one threshold voltage V.sub.T of the pass transistor M.sub.p of the DRAM cells 100. The voltage level V.sub.h will activate the pass transistor M.sub.p of the DRAM cells 100 of FIGS. 1a and 1b with the voltage drop that is equal to threshold voltage V.sub.T of the pass transistor M.sub.p of the DRAM cells 100. The charge present on the cell capacitor C.sub.c of the DRAM cell 100 of FIGS. 1a and 1b will flow to or from the bit line BL 105.
The latching sense amplifier 125 will be activated to sense the change in voltage on the bit line BL 105 due to the selection of the DRAM cell 100 on the word line WL3 115c. The latching sense amplifier 125 will drive the bit line BL 105 to either the voltage level of the power supply voltage source V.sub.cc or the voltage level of the ground GND. The level of the bit line BL 105 is dependent upon the level of charge present on the cell capacitor C.sub.c of the DRAM cell 100. The latching sense amplifier 125 further will drive the bit line BL 110 to either the voltage level of the power supply voltage source V.sub.cc or the voltage level of the ground GND that is opposite that of the bit line BL 105.
This forcing both primary and complementary bit lines BL 105 and BL 110 to the voltage level difference between the voltage level of the power supply voltage source V.sub.cc and the voltage level of the ground GND is a well known source of noise, as is described in M. Aoki, et al., "A 60 ns 16 Mb CMOS DRAM with a transposed data-line structure", IEEE Trans. Solid-state Circuits, SC-23, No.5, p. 1113, 1988. As semiconductor processing technology has improved, the size of the DRAM cell 100 has been decreasing. This has increased impact of the noise to a point that it is becoming a serious source of data errors.
U.S. Pat. No. 5,276,641 (Sprogis et al) describes an open/folded bit line sense amplifier arrangement and accompanying circuit for a DRAM array. The basic structure consists of two memory arrays, each with a plurality of memory cells. These memory arrays employ a special cell layout architecture in which each cell shares only one passing word line with an adjacent cell. The memory cells are interconnected by bit lines which are parallel to each other and word line which are perpendicular to the bit lines. Between the two memory arrays, arranged in a column, is a set of open sense amplifiers. Each open sense amplifier has a connector on either side for respectively accessing each of the two memory arrays. One of the connectors multiplexed to preferably three adjacent bit lines of on array while the other connector is multiplexed to preferably three adjacent bit lines of the opposite array. On the outer side of each memory array at the opposite ends of the bit lines is a set of folded bit line sense amplifiers, each having two connectors which are multiplexed to preferably three adjacent bit lines in the array one of the bit lines being common to each of these connectors. When data is to be input or output from the memory cells in an array, a word line is activated. In such a selected array, the connectors of each of the folded bit line sense amplifiers are connected by the multiplexing circuitry to one bit line in that array. An intervening bit line separates the two bit lines to which they are connected. Simultaneously, the connectors of an open bit line sense amplifier are activated, on being connected to a bit line in the selected array and the other being connected to a bit line in the unselected array, the later being surrounded on either side by bit lines clamped to AC ground, thus balancing the open sense amplifier capacitively and thereby greatly reducing bit-line coupling noise.
U.S. Pat. No. 5,625,585 (Ahn et al.) describes a bit line structure that has low power consumption. The bit line structure will allow reduced chip operating current without expanding the layout area. Further the sensing noise between bit lines can be reduced compared with the conventional methods.
The bit line structure has a plurality of sense amplifiers each connected to two pairs of bit lines BL and /BL through bit line selecting switches. A plurality of memory cells are connected to the bit lines BL and /BL. A first bit line pair BL and /BL and a second bit line pair BL and /BL are formed by dividing a bit line disposed within a same line respectively in a cell array. A first connecting bit line will connect the bit line BL of said second bit line pair to the sense amplifier, and a second connecting bit line will connect the bit line /BL of the second bit line pair to the sense amplifier. The second connecting bit line will have two crossing sections crossing with another second connecting bit line for connecting a bit line BL of a second bit line belonging to an adjacent sense amplifier. The bit line selecting switches connect the first bit line pair and the second bit line pair respectively to the sense amplifier. The number of memory cells connected to each bit line is reduced to 1/2 compared with the conventional technique. The bit lines are arranged 3-dimensionally to eliminate the area loss in carrying out the layout, and particularly, the connecting bit lines are made of a conductive material, which has a smaller resistance than a conductive material of the bit lines.
The second connecting bit line passes over the first bit line of the bit line BL of another sense amplifier, and among the two crossing points one of them is located between the sense amplifier and the bit line selecting switch. The first and second connecting bit lines are composed of a material different from that of the first and second bit lines.
U.S. Pat. No. 5,010,523 (Yamauchi) discloses a sensing circuit for a DRAM. The bit lines of the DRAM array that are the reference side are temporarily connected to a large load capacitance or to a pre-charge power source when a read operation is performed. This will prevent change in electric potential of the bit lines at the reference side occurring due to interference noises between the bit lines from effecting a read operation. Connecting the reference side of the bit lines to the large load capacitance or to the pre-charge power source will further prevent deterioration of a signal-to-noise ratio due to the change in electric potential of the bit lines.
U.S. Pat. No. 5,627,789 (Kalb, Jr.) describes a differential voltage memory apparatus, which includes one or more preliminary stages of differential amplifiers, which operate prior to triggering of a final stage of differential amplifiers. The preliminary stages of differential amplifiers include cross-coupled inverters that are closely coupled to bit lines connected to memory cells of the memory array. The final stage of sense amplifiers include cross-coupled inverters which are, when in use, substantially decoupled from the bit lines of the memory cells. The preliminary sense amplifiers are activated shortly after activation of corresponding memory cells and provide an initial stage of amplification of a voltage differential generated by the memory cells. The final stage sense amplifiers are triggered after a suitable time delay guaranteeing that a sufficient minimum voltage differential has been generated. The preliminary sense amplifier stages, which are closely coupled to the bit lines and are thereby subject to heavy capacitive loading. These capacitive loaded preliminary sense amplifier stages provide an initial stage of amplification which is substantially decoupled from noise effects, such as effects caused by alpha strikes and the like. The final stage of sense amplifiers, which are substantially decoupled from the capacitive bit lines, are coupled to the preliminary sense amplifier stages to quickly amplify the voltage differential to opposing rail voltages.